Self-Timed SRAM with Smart Latency Bundling Self-Timed SRAM with Smart Latency Bundling

In energy-aware design, especially for systems with uncertain power sources, asynchronous computation loads which can function under variable power supply have many potential advantages. Fully safe asynchronous loads based on delay insensitivity (DI), however, tend to suffer power and size penalties. As a compromise, delay bundling has been widely used in asynchronous computation, but traditional delay elements have been shown to be unsuitable for bundling memory components, whose latency behaviour varies differently under variable Vdd from other types of logic. This paper proposes an intelligent delay bundling method for SRAM working under Vdd which unpredictably varies over a wide range (e.g. 200mV to 1V for 90nm technology), based on the principle of using matching delay bundling elements. A fully speed independent (SI) SRAM design is investigated in depth and a self-timed SRAM architecture using such SI SRAM cells as delay bundling elements is demonstrated through comprehensive analysis. Keywords-component; SRAM, failure rate, energy harvesting systems, timing variations.